1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device formed on a semiconductor substrate and more particularly to a MOS type field effect transistor (FET) having its source/drain regions raised higher than a surface of the semiconductor substrate.
2. Related Art
Down-sizing of a MOS type FET which is a main constitutional element of a high integration density semiconductor integrated circuit is being enhanced with the increase in integration density. It is said that, with a gate length of such MOS type FET being in the order of 0.1 .mu.m, junction depth of a source/drain difflusion layer should be made in the order of 50 nm. In such a down-sized MOS type FET, problems related to the short-channel effects and/or the punch-through are becoming serious.
A source/drain region having a small junction depth is usually formed by ion implantation. The simplest method of forming a shallow diffusion layer by ion implantation is to reduce the acceleration energy of ions to thereby shorten the penetration depth (projection range) of ions during ion implantation. However, when the acceleration energy is reduced, the amount of ion current during ion implantation is reduced, resulting in a problem that the method becomes unsuitable for mass-production.
Further, it may be considered to restrict diffusion of impurity by lowering a temperature of thermal treatment for activation of implanted ions. However, it is well known that boron which is a P-type impurity tends to be recombined with point defects in a silicon substrate resulting in defect enhanced diffusion. Therefore, even when the thermal treatment temperature is reduced, it is impossible to suppress the diffusion depth to a small value.
In order to make up for the problem of defect enhanced diffusion, a rapid thermal annealing (RTA) for performing heat treatment within a short time has been proposed. However, it is known that, even with RTA, a practical junction depth of the diffusion layer is 80 to 100 nm, which is still larger than 50 nm at which the influences of the short-channel effects and the punch-through can be suppressed. Further, even with RTA, the diffusion of boron impurities is predominantly by the aforementioned defect enhanced diffusion. It has been known that the defect enhanced diffusion is influenced by the ramp-up rate during the rapid heating process. Thus, there is a further problem that precise control of the junction depth among different wafers is difficult due to the variation in the ramp up rate from wafer to wafer.
Further, in the conventional ion implantation, when the junction depth of a diffusion layer is made small, there may be a problem that resistance of the diffusion layer and contact resistance to a wiring are increased.
In order to solve these problems, a fabrication method of a MOS type FET having an elevated (or raised) diffusion layer has been proposed in Japanese Laid-open Patent Application No. H2-222153, in which a silicon layer is selectively formed on a diffusion layer of a silicon substrate. The proposed fabrication method of a MOS type FET having a raised diffusion layer structure will be described with reference to FIG. 4(a) to FIG. 4(c).
First, as shown in FIG. 4(a), an element separating oxide film 2 is formed on a silicon substrate 1A by partial oxidation of a surface of the substrate. A well region 1B is formed by introducing an impurity into the substrate 1A up to several microns deep by ion implantation and activating the impurity ion by the rapid thermal annealing RTA) at about 850.degree. C. Then, a gate oxide film 3 having thickness in the order of 5 nm is formed on a surface of the well region 1B and a boron containing polysilicon layer 200 nm thick is deposited on the gate oxide film 3. The polysilicon layer later forms a gate electrode. Then, an oxide film 50 nm thick is deposited thereon and a gate electrode 4 is formed by patterning the polysilicon layer with using the oxide film as a mask. Thereafter, a nitride film 20 nm thick is deposited on the well region and a sidewall 5 is formed by removing the nitride film other than that adjacent a gate sidewall portion by plasma etching.
Then, after a native oxide film on a portion of the well region in which a source/drain region is to be formed is removed by processing the wafer in hydrofluoric acid vapor, the wafer is set in a low pressure CVD device without exposing it to atmosphere and an epitaxial silicon layer 6A is selectively grown on only the surface of the well region in which silicon is exposed and the source/drain region is to be formed (FIG. 4(b). This selective epitaxy is performed at about 800.degree. C. by flowing a gas mixture of dichlorosilane (SiCl.sub.2 H.sub.2) as a material gas, hydrogen (H.sub.2) as a carrier gas with hydrogen chloride gas. Thus, it is possible to grow the silicon layer 6A on only the silicon surface without formation of silicon film on the silicon oxide film. During the selective epitaxial growth of the silicon layer, a formation of silicon layer on a surface of the gate electrode 4 in which polysilicon is exposed can be prevented by covering the surface of the gate electrode 4 with an oxide film 6C. The oxide film 6C is removed thereafter. Depending on the selective growing condition, there may be a case where a silicon layer is not grown in the vicinity of the sidewall 5 and a facet 7 which prevents the selectively grown silicon layer from contacting with the sidewall 5 is formed. In such a case, in order to bury the facet 7, a second sidewall 8 of such materials as silicon nitride is formed as shown in FIG. 4(b).
Then, in order to prevent contamination of the wafer due to ion implantation, an oxide film about 5 nm thick (not shown) is formed on the surface of the gate electrode 4 and a surface of an ion implantation region which is the surface of the silicon layer 6A by thermal oxidation. Thereafter, impurity ions are introduced into the region in which the source/drain is to be formed, by ion implantation. The ion implantation is performed using BF.sub.2 with injection energy of 10 to 20 keV when the conductivity type of the source/drain region is to be P type, or by using As (arsenic) with injection energy of 40 to 60 keV when the conductivity type thereof is to be N type. The impurity implanted is activated by rapid thermal annealing (RTA) at a temperature in the order of 1,000.degree. C. and diffuses throughout the gate electrode 4 and into the well region 1B in which the source/drain region is to be formed, resulting in source and drain regions 9.
Then, after the oxide film (not shown) for preventing the contamination due to ion implantation is removed, a titanium (Ti) layer 40 nm thick is formed by sputtering and a titanium silicide (TiSi.sub.2) film having a relatively high resistance is formed on the silicon layer 6 and the gate electrode 4 by RTA at about 700.degree. C. The titanium layer on the oxide film is not silicified during the heat treatment by rapid thermal annealing (RTA) and remains as it is. After titanium is selectively etched away leaving only titanium silicide, the high resistance titanium silicide film (TiSi.sub.2) is converted into low resistance titanium silicide films 10A and 10B through phase transfer by RTA at about 850.degree. C.
Further, an interlayer film 11 of such insulating material as silicon oxide is deposited on the wafer by a low temperature growth method such as plasma CVD, contact holes 12 are opened in the interlayer film 11 and an aluminum wiring 13 is formed through the contact holes, resulting in a MOS type FET as shown in FIG. 4(c).
In the case of a MOS type FET, the junction depth Xj of source/drain diffusion regions 9, which influences the electric characteristics of the transistor, is measured from a surface of a silicon substrate thereof. In a case of MOS type FET having the raised source/drain structure, ion implantation is performed from the surface of the raised layer 6A of the source/drain region, so that it is possible to reduce the junction depth Xj by an amount corresponding to the thickness of the raised layer 6A. Therefore, the raised source/drain structure is suitable for obtaining a MOS type FET having small junction depth.
In more detail, when an RTA condition under which a conventional MOS type FET having no raised structure and having junction depth Xj of 100 nm can be formed is applied to a MOS type FET having 60 nm-raised structure, the junction depth Xj can be made in the order of 40 nm. Therefore, it is possible to easily obtain a down-sized MOS type FET having junction depth Xj of 0.1 .mu.m. Another merit of this raised structure resides in that sheet resistance of the source/drain region and contact resistance can be reduced by an amount corresponding to the extra thickness of the raised layer.
On the other hand, as mentioned previously, it is impossible to prevent the influence of defect enhanced diffusion of boron and to prevent a wafer to wafer variation in diffusion depth, even when rapid thermal annealing is used. In order to prevent the influence of the defect enhanced diffusion of boron and to prevent a variation of diffusion depth, a simultaneous injection of boron and carbon and a subsequent heat treatment have been studied. Since carbon has a stronger tendency to combine with excess point defects in a silicon substrate than boron, it is possible to reduce combination of boron with point defects in silicon to thereby reduce defect enhanced diffusion of boron.
In the case where carbon is implanted simultaneously with implantation of boron, there is a problem that junction leakage increases due to residual defects formed during carbon implantation since carbon distribution has an edge close to a PN junction.
Moreover, surface concentration of carbon needs to be in the order of 10.sup.19 atoms/cm.sup.3. In such a case, a concentration distribution 26B of implanted boron is controlled to be shallower than a concentration distribution 26C of implanted carbon, as shown in FIG. 5. Thereafter, boron is diffused by heat treatment, resulting in a source/drain region. Since, in such a case, a precise control of concentration distribution of carbon is difficult and defect enhanced diffusion of boron extends outside the concentration distribution of carbon when the latter is narrow, there is a problem that a variation of junction depth Xj occurs and it is impossible to make the junction depth Xj sufficiently small.